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2001 mos integrated circuit pd3768 7500 pixels 3 color ccd linear image sensor data sheet document no. s15418ej3v0ds00 (3rd edition) date published february 2006 ns cp (n) printed in japan 2001 the mark shows major revised points. the revised points can be easily searched by copying an "" in the pdf file and specifying it in the "find what:" field. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. description the pd3768 is a high-speed and high sensitive color ccd (charge coupled device) linear image sensor which changes optical images to electrical signal and has the function of color separation. the pd3768 has 3 rows of 7500 pixels, and it is a 2-outpu t/color type ccd sensor with 2 rows/color of charge transfer register, which transfers the photo signal electrons of 7500 pixels separately in odd and even pixels. therefore, it is suitable for 600 dpi/a3 high-speed color digital copiers, color scanners and so on. features ? valid photocell : 7500 pixels 3 ? photocell pitch : 9.325 m ? line spacing : 37.3 m (4 lines) red line - green line, green line - blue line ? color filter : primary colors (red, green a nd blue), pigment filter (with light resistance 10 7 lx?hour) ? resolution : 24 dot/mm a3 (297 420 mm) size (shorter side) ? drive clock level : cmos output under 5 v operation ? data rate : 44 mhz max. (22 mhz/1 output) ? output type : 2 outputs in phase/color ? power supply : +10 v ? on-chip circuits : reset feed-through level clamp circuits voltage amplifiers ordering information part number package pd3768d-az ccd linear image sensor 36-pin ceramic dip (cerdip) (15.24 mm (600)) remark the pd3768d-az is a lead-free product.
data sheet s15418ej3v0ds 2 pd3768 block diagram 8 13 14 5 3 1 36 34 32 30 29 23 28 16 24 22 21 15 cp 2l gnd 20 2a 1b (blue) tg1 (blue) tg2 (green) tg3 (red) v out 2 (blue, even) v out 1 (blue, odd) v out 3 (green, odd) v out 4 (green, even) v out 6 (red, even) v out 5 (red, odd) 1a 2b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . photocell transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s1 s2 s7499 s7500 d129 d140 (green) photocell transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s1 s2 s7499 s7500 d129 d140 (red) photocell transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s1 s2 s7499 s7500 d129 d140 2l ? 7 r 4 2 35 33 31 v od gnd gnd gnd gnd 9 10 6 v od
data sheet s15418ej3v0ds 3 pd3768 pin configuration (top view) ccd linear image sensor 36-pin ceramic dip (cerdip) (15.24 mm (600)) ? pd3768d-az red green blue 1 1 1 7500 7500 7500 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 v out 4 gnd v out 6 gnd v out 5 v od 2l 10 nc nc nc 1a 2b tg3 gnd nc nc output signal 4 (green, even) ground output signal 6 (red, even) ground output signal 5 (red, odd) output unit drain voltage shift register clock 10 last stage shift register clock no connection no connection no connection shift register clock 1a shift register clock 2b transfer gate clock 3 (for red) ground no connection no connection output signal 3 (green, odd) ground output signal 1 (blue, odd) ground output signal 2 (blue, even) output unit drain voltage reset feed-through level clamp clock last stage shift register clock shift register clock 20 no connection no connection no connection shift register clock 2a shift register clock 1b transfer gate clock 1 (for blue) transfer gate clock 2 (for green) no connection no connection v out 3 gnd v out 1 gnd v out 2 v od cp 2l 20 nc nc nc 2a 1b tg1 tg2 nc nc 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 r reset gate clock caution connect the no connection pins (nc) to gnd. photocell structure diagram photocell array structure diagram (line spacing) 9.325 m 6.325 m m 3 channel stopper aluminum shield blue photocell array 9.325 m 9.325 m 9.325 m green photocell array red photocell array 4 lines (37.3 m) 4 lines (37.3 m)
data sheet s15418ej3v0ds 4 pd3768 absolute maximum ratings (t a = + 25 c) parameter symbol ratings unit output drain voltage v od ? 0.3 to + 12 v shift register clock voltage v 1 , v 2 ? 0.3 to + 8 v last gate shift register clock voltage v 2l ? 0.3 to + 8 v reset gate clock voltage v r ? 0.3 to + 8 v clamp clock voltage v cp ? 0.3 to + 8 v transfer gate clock voltage v tg1 to v tg3 ? 0.3 to + 8 v operating ambient temperature note t a ? 25 to + 60 c storage temperature t stg ? 40 to + 100 c note use at the condition without dew condensation. caution product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefor e the product must be used under conditions that ensure that the absolute maxi mum ratings are not exceeded. recommended operating conditions (t a = + 25 c) parameter symbol min. typ. max. unit output drain voltage v od 9.5 10.0 10.5 v shift register clock high level v 1h , v 2h 4.5 5.0 5.5 v shift register clock low level v 1l , v 2l ? 0.3 0 + 0.5 v last gate shift register clock high level v 2lh 4.5 5.0 5.5 v last gate shift register clock low level v 2ll ? 0.3 0 + 0.5 v reset gate clock high level v rh 4.5 5.0 5.5 v reset gate clock low level v rl ? 0.3 0 + 0.5 v clamp clock high level v cph 4.5 5.0 5.5 v clamp clock low level v cpl ? 0.3 0 + 0.5 v transfer gate clock high level v tg1h to v tg3h 4.5 v 1h note v 1h note v transfer gate clock low level v tg1l to v tg3l ? 0.3 0 + 0.5 v data rate 2f r 1 2 44 mhz note when transfer gate clock high level (v tg1h to v tg3h ) is higher than shift register clock high level (v 1h ), image lag can increase.
data sheet s15418ej3v0ds 5 pd3768 electrical characteristics t a = + 25 c, v od = 10 v, f r = 1 mhz, data rate = 2 mhz, storage time = 10 ms, input signal clock = 5 v p-p , light source (except response1) : 2950 k halogen lamp + cm-500s (infrared cut filter, t = 1 mm) parameter symbol test conditions min. typ. max. unit saturation voltage v sat 1.5 2.0 ? v red ser 2950 k halogen lamp + cm-500s ? 0.14 ? lxs green seg ? 0.13 ? lxs saturation exposure blue seb ? 0.26 ? lxs photo response non-uniformity prnu v out = 1.0 v ? 6.0 18.0 % photo response non-uniformity at low illumination prnu2 v out = 0.1 v ? 6.0 18.0 % average dark signal ads light shielding, data rate = 2 mhz, storage time = 10 ms ? 1.0 5.0 mv dark signal non- uniformity dsnu light shielding, data rate = 2 mhz, storage time = 10 ms ? 3.0 12.0 mv power consumption p w ? 700 900 mw output impedance z o ? 0.2 0.4 k ? red r r 3200 k halogen lamp + c-500s 15.4 22.0 28.6 v/lxs green r g + ha-50 12.6 18.0 23.4 v/lxs response1 blue r b 5.6 8.0 10.4 v/lxs red r r 2950 k halogen lamp + cm-500s 9.8 14.0 18.2 v/lxs green r g 10.7 15.3 19.9 v/lxs response2 blue r b 5.3 7.6 9.9 v/lxs image lag il v out = 500 mv ? 40 80 mv image lag color difference il-dif v out = 500 mv ? 5 20 mv image lag o/e il-o/e v out = 500 mv ? 10 30 mv offset level note 1 v os 3.8 4.5 5.2 v output fall delay time note 2 t d ? 14 ? ns register imbalance ri v out = 1.0 v ? 0 5 % total transfer efficiency tte v out = 1.0 v, f r = 22 mhz 94 98 ? % red ? 630 ? nm green ? 540 ? nm response peak blue ? 445 ? nm dr1 v sat /dsnu ? 666 ? times dynamic range dr2 v sat / dark ? 870 ? times reset feed-through noise rftn light shielding ? 1000 ? 200 + 500 mv light shielding random noise dark bit clamp, t17 = 10 ns ? 2.3 ? mv notes 1. refer to timing chart 2 and timing chart 4 . 2. t d is defined as periods from 10% of 2l to 10% of v out 1 to v out 6 (refer to application curcuit example ).
data sheet s15418ej3v0ds 6 pd3768 input pin capacitance (t a = + 25 c, v od = 10 v) parameter symbol pin pin no. min. typ. max. unit shift register clock pin capacitance c 1 10 9 ? 330 450 pf 1a 13 ? 330 450 pf 1b 23 ? 330 450 pf c 2 2b 14 ? 330 450 pf 2a 24 ? 330 450 pf 20 28 ? 330 450 pf last stage shift register clock pin capacitance c l 2l 8 ? 10 20 pf 29 ? 10 20 pf reset gate clock pin capacitance c r r 7 ? 10 20 pf clamp clock pin capacitance c cp cp 30 ? 10 20 pf transfer gate clock pin capacitance c tg tg1 22 ? 100 150 pf tg2 21 ? 100 150 pf tg3 15 ? 100 150 pf
data sheet s15418ej3v0ds 7 pd3768 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 120 122 124 126 128 130 132 7626 7628 7630 7632 7634 7636 7638 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 119 121 123 125 127 129 131 7625 7627 7629 7631 7633 7635 7637 v out 1, 3, 5 v out 2, 4, 6 r cp note invalid photocell (6 pixels) invalid photocell (6 pixels) valid photocell (7500 pixels) optical black (96 pixels) 10, 1a, 1b 20, 2a, 2b 2l tg1 to tg3 note timing chart 1 (bit clamp mode, for each color) note set the r and cp pulse to low level during this period.
data sheet s15418ej3v0ds 8 pd3768 timing chart 2 (bit clamp mode, for each color) v out 1 to v out 6 cp r 10, 1a, 1b 20, 2a, 2b 90% 10% 2l 90% 90% 10% 10% 10% rftn v os t6l t7l t8 t9 t16 t13 t14 t12 t17 t10 t15 t d 90% 90% 10% 10% t6 t7 + ? symbol min. typ. max. unit t6, t7 0 50 ? ns t6l, t7l 0 5 ? ns t8, t10 0 5 ? ns t9 10 125 ? ns t12, t14 0 5 ? ns t13 10 125 ? ns t15 0 250 ? ns t16 8 125 ? ns t17 8 125 ? ns
data sheet s15418ej3v0ds 9 pd3768 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 120 122 124 126 128 130 132 7626 7628 7630 7632 7634 7636 7638 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 119 121 123 125 127 129 131 7625 7627 7629 7631 7633 7635 7637 v out 1, 3, 5 v out 2, 4, 6 r cp note invalid photocell (6 pixcels) invalid photocell (6 pixels) valid photocell (7500 pixels) optical black (96 pixels) 2l tg1 to tg3 note 10, 1a, 1b 20, 2a, 2b note set the r and cp pulse to low level during this period. timing chart 3 (line clamp mode, for each color)
data sheet s15418ej3v0ds 10 pd3768 timing chart 4 (line clamp mode, for each color) v out 1 to v out 6 cp r 90% 10% 2l 90% 10% 10% rftn v os t6l t7l t8 t9 t10 t20 t d 90% 90% 10% 10% t6 t7 + ? 'l' 10, 1a, 1b 20, 2a, 2b symbol min. typ. max. unit t6, t7 0 50 ? ns t6l, t7l 0 5 ? ns t8, t10 0 5 ? ns t9 10 125 ? ns t20 5 250 ? ns
data sheet s15418ej3v0ds 11 pd3768 timing chart 5 (bit clamp mode, line clamp mode, for each color) r cp note 2l tg1 to tg3 10, 1a, 1b 20, 2a, 2b 90% 90% 10% t4 t3 t2 t1 90% 90% 10% 10% t8 t9 t5 t16 t13 t14 t12 t17 t10 t15 symbol min. typ. max. unit t1, t5 200 300 ? ns t2, t4 0 50 ? ns t3 3000 5000 ? ns t8, t10 0 5 ? ns t9 10 125 ? ns t12, t14 0 5 ? ns t13 10 125 ? ns t15 0 250 ? ns t16 8 125 ? ns t17 8 125 ? ns note set the r and cp pulse to low level during this period.
data sheet s15418ej3v0ds 12 pd3768 10, 20 cross points 10 20 2.0 v or more 2.0 v or more 1a, 2a cross points 1a 2a 2.0 v or more 2.0 v or more 1b, 2b cross points 1b 2b 2.0 v or more 2.0 v or more 10, 2l cross points 10 2l 2.0 v or more 0.5 v or more remark adjust cross points ( 10, 20), ( 1a, 2a), ( 1b, 2b) and ( 10, 2l) with input resistance of each pin.
data sheet s15418ej3v0ds 13 pd3768 definitions of characteristic items 1. saturation voltage : v sat output signal voltage at whic h the response linearity is lost. 2. saturation exposure : se product of intensity of illumination (lx) and storag e time (s) when saturation of output voltage occurs. 3. photo response non-uniformity : prnu the output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. this is calculated by the fo llowing formula, and it is defined by each six of them. 4. average dark signal : ads average output signal voltage of all the va lid pixels at light shielding. this is calculated by the following formula, and it is defined by each six of them. x register dark dc level v out x ? ads (mv) = d j : dark signal of valid pixel number j 7500 j = 1 7500 d j prnu (%) = x = x j : output voltage of valid pixel number j x x : maximum of ? x j ? x ? x 7500 j=1 7500 x j 100 ? ?
data sheet s15418ej3v0ds 14 pd3768 5. dark signal non-uniformity : dsnu absolute maximum of the difference between ads and vo ltage of the highest or lowest output pixel of all the valid pixels at light shielding. this is calculated by the following formula, and it is defined by each six of them. 6. output impedance : z o impedance of the output pins viewed from outside. 7. response : r output voltage divided by exposure (lxs). note that the response varies with a light source (spectral characteristic). 8. image lag : il the rate between the last output voltage and the next one after read out the data of a line. 9. image lag color difference : il-dif it is defined as a difference between colors of the average of image lag. it is expressed with the next expression to be concrete. v out tg light v out on off v 1 ads dsnu register dark dc level v out il (mv) = v 1 (v out = 500 mv) | (average of image lag of blue output) | (average of image lag of green output) | (average of image lag of red output) (average of image lag of green output) | (average of image lag of red output) | (average of image lag of blue output) | ? ? ? d j : dark signal of valid pixel number j dsnu (mv) : maximum of ? d j ? ads ? j = 1 to 7500
data sheet s15418ej3v0ds 15 pd3768 10. image lag o/e : il-o/e it is defined as a difference of the average of image lag of odd and even pixels for each color. 11. register imbalance : ri the rate of the difference between the averages of the out put voltage of odd and even pixels, against the average output voltage of all the valid pixels. 12. total transfer efficiency : tte the total transfer rate of ccd analog shift register. this is calculated by the following formula, it is difined by each output. tte (%) = (1 ? v b / average output of all the valid pixels) 100 v a ? 1 : the last pixel output ? 1 (odd pixel: 7631th pixel) v a : the last pixel output (odd pixel: 7633th pixel) v b : the spilt pixel output (odd pixel: 7635th pixel) v a ? 1 v a v b 13. light shielding random noise : dark light shielding random noise dark is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). this is measured by the dc level sampling of only the signal level, not by cds (correlated double sampling). v 1 v 100 v 2 line 2 line 100 line 1 v out ri (%) = 2 n j = 1 j = 1 n 2 (v 2j ?1 ? v 2j ) 1 n n v j 100 n v j : number of valid pixels : output voltage of each pixel dark (mv) = , v = i = 1 100 (v i ? v) 2 i = 1 100 v i 100 100 1 v i : a valid pixel output signal among all of the valid pixels for each color
data sheet s15418ej3v0ds 16 pd3768 standard characteristic curves (reference value) dark output temperature characteristic storage time output voltage characteristic (t a = +25 c) operating ambient temperature t a ( c) storage time (ms) 8 4 2 1 0.5 0.25 0.1 10 0 20304050 relative output voltage relative output voltage 2 1 0.2 0.1 1510 wavelength (nm) response ratio (%) total spectral response characteristics (without infrared cut filter and heat absorbing filter) (t a = +25 c) 400 500 600 700 100 80 60 40 20 0 b b g r g
data sheet s15418ej3v0ds 17 pd3768 application circuit example v out 3 gnd v out 4 v out 1 v out 6 v out 2 v out 5 gnd gnd gnd v od r nc v od cp nc nc nc nc 2a nc 1a 2b gnd nc nc 1b tg1 nc nc tg2 tg3 10 20 2l pd3768 + 10 f/16 v 0.1 f + 47 f/25 v 0.1 f +5 v +10 v + 10 f/16 v 0.1 f +5 v b4 b6 b5 b1 b3 b2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 2 ? 2 ? 2 ? 2 ? 2 ? 2 ? 2 ? 2 ? 47 ? 47 ? 47 ? 47 ? 2 ? 10 ? 2a tg2 cp 10 tg3 ? ? 2l r 2b 1a 1b tg1 2l 20 2l caution connect the no connection pins (nc) to gnd. remarks 1. connect two inverters (74ac04) to each 10, 1a, 1b, 20, 2a, 2b pin. 2. inverters shown in the above application circuit example are the 74ac04. 3. b1 to b6 in the application circuit example are shown in the figure below. +10 v 110 ? 4.7 k ? 47 f/25 v 2sa1005 2sc945 1 k ? 47 ? + ccd v out b1-b6 equivalent curcuit
data sheet s15418ej3v0ds 18 pd3768 package drawing ccd linear image sensor 36-pin ceramic dip (15.24 mm (600)) 36d-1ccd-pkg3-1 refractive index dimension name 1.5 91.0 9.0 1.1 glass cap 1 1st valid pixel center of package 2 the bottom of package the surface of the chip 3 the surface of the chip the surface of the glass cap 4 the tolerance of packge dimension 0.25 : less than 10 mm from w/f edge 0.50 : equal or more than 10 mm from w/f edge 94.0 0.7 14.66 4 3.0 0.1 1.28 0.1 3.00 0.08 1.0 0.08 26.0 0.2 24.13 0.20 20.32 0.13 20.32 0.13 48.26 0.40 7.33 0.3 0.25 0.05 2.4 0.3 2 3.85 0.38 2.54 0.13 2.0 0.2 5.0 0.2 1.27 0.46 (5.0) (1.8) (17.09 max.) (15.24 min.) (2.6) 3 33.3 0.6 1 the 1st valid pixel
data sheet s15418ej3v0ds 19 pd3768 recommended soldering conditions when soldering this product, it is highly recommended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. type of through-hole device pd3768d-az : ccd linear image sensor 36-pi n ceramic dip (cerdip) (15.24 mm (600)) process conditions partial heating method pin temperature : 300 c or below, heat time : 3 seconds or less (per pin) cautions 1. during assembly care should be taken to prevent solder or fl ux from contacting the glass cap. the optical characteristics could be degraded by such contact. 2. soldering by the so lder flow method may have deleterious effects on prevention of glass cap soiling and heat resistance. so the method cannot be guaranteed.
data sheet s15418ej3v0ds 20 pd3768 notes on handling the packages mounting of the package glass cap the application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. particular care should be taken when mounting the package on the circuit board. don't have any object come in contact with glass cap. you should not reform the lead frame. we recommended to use a ic-inserter when you assemble to pcb. also, be care that the any of the following can cause the package to crack or dust to be generated. 1. applying heat to the external leads for an extended period of time with soldering iron. 2. applying repetitive bending stress to the external leads. 3. rapid cooling or heating for this product, the reference value for the three-point bending strength note is 180 [n] (at distance between supports: 70 mm), is 500 [n] (at distance between supports: 26 mm). avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic). note three-point bending strength test distance between supports: 70 mm or 26 mm, support r: r 2 mm, loading rate: 0.5 mm/min. don?t either touch glass cap surface by hand or have any object come in contact with glass cap surface. care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. for dirt stuck through electricity ionized air is recommended. 1 2 70 mm load load 70 mm 26 mm load load 26 mm
data sheet s15418ej3v0ds 21 pd3768 notes on handling the packages operate and storage environments 3 operate in clean environments. ccd image sensors are precise optical equipment that should not be subject to mechanical shocks. exposure to high temperatures or humidity will affect the characteristics. so avoid storage or usage in such conditions. keep in a case to protect from dust and dirt. dew condensation may occur on ccd image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. avoid such rapid temperature changes. for more details, refer to our document "review of quality and reliability handbook" (c12769e) electrostatic breakdown ccd image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. before handling be sure to take the following protective measures. 1. ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. either handle bare handed or use non-chargeable gloves, clothes or material. 4. ionized air is recommended for discharge when handling ccd image sensor. 5. for the shipment of mounted substrates, use box treated for prevention of static charges. 6. anyone who is handling ccd image sensors, mounting them on pcbs or testing or inspecting pcbs on which ccd image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 m ? . 4
data sheet s15418ej3v0ds 22 pd3768 [ memo ]
data sheet s15418ej3v0ds 23 pd3768 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
pd3768 the information in this document is current as of february, 2006. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec e lectronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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